COMP 182: Quiz 5 – Memory

Quiz 5: Memory

Question 1

Multi-level memory hierarchy from fastest to slowest: Registers -> L1 cache -> L2 cache

Question 2

L1 cache is refilled directly, first from: L2 cache

Question 3

RISC CPU’s L1 cache architecture is: Separate I and D caches (Harvard),

Question 4

RISC CPU’s L2 cache architecture is: Unified caches (von Neumann),

Question 5

RISC CPU’s L3 cache architecture is: Shared unified cache,

Question 6

Each level of cache memory is approx. N times larger/smaller and faster/slower where N=: 10,

Question 7

Cache memory is made from what type of memory: SRAM,

Question 8

Cache memory in most RISC CPU’s now use what type of mapping: set associative,

Question 9

Cache is refilled in one chunk at a time, called a: block,

Question 10

D-Cache misses in RISC can only be caused by which type of instruction: Load or Store,

Question 11

D-Cache organization that has the simplest hardware implementation: Direct-mapped, Write-through,

Question 12

I-Cache misses in RISC are most likely to be caused by which type of instruction: Jump,

Question 13

Virtual memory is most likely to be needed in which class of computer system: Desktop computer or Server,

Question 14

Virtual memory is used by an OS to do this: Any of these,

Question 15

Virtual memory uses a Page Table with an on-chip cache called a: TLB

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