COMP 182 Quiz 6 – Interrupts, PSW, Registers, Clocks

Quiz 6 – Interrupts, PSW, Registers, Clocks

Question 1

Interrupts have all these properties, except: Cause no pipeline flush,

Question 2

Low priority devices should use what class of Interrupt: Vectored,

Question 3

What is an Interrupt Vector: All of these

Question 4

Interrupts are processed if what conditions are met: Mask and global enable bits are set, it is pending and highest priority

Question 5

PSW contains: Program Status Word

Question 6

MIPS PSW contains: All of these,

Question 7

MIPS CPO contains a Cause register, which contains: Exception code + interrupts pending,

Question 8

MIPS CPO contains which registers: all of these,

Question 9

Registers are composed of a linear array of what logic element: D flip-flops,

Question 10

Which sequential logic element is clock-edge triggered: Flip-flops,

Question 11

Which clocking scheme helps keep a digital system tightly synchronized (even used in the 18080): 2-phase clocking,

Question 12

What type of logic block is necessary for an FSM – Finite State Machine: Registers,

Question 13

What type of analog circuit is necessary for providing a stable clock: PLL, including a VCXO,

Question 14

What is used to distribute a system clock to all of the system: PLL tree,

Question 15

System clock stability and skew both impact: Timing margins

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